1. Technical Field
The present invention relates generally to energy management in processing systems, and more particularly, to energy management within a multi-threaded processing system.
2. Description of the Related Art
Present-day computing systems include both single-threaded (uniprocessor) processing systems and simultaneous multi-threaded (SMT) processing systems. In the past, SMT processing systems have typically been restricted to large server systems and dedicated mainframe systems, but with the advent of desktop computer operating systems that support multiple simultaneous thread execution and processor technology that permits integration of multiple processor cores within a single integrated circuit, SMT processors are likely to appear within desktop and notebook computing systems in the very near future. In large fixed-location systems and small portable systems, energy management has become increasingly important for battery energy management in portable systems, and for power dissipation management in all computing systems. Recent designs push the envelope of power dissipation both within processor integrated circuits, and within the total system package.
SMT processors provide very efficient use of processor resources, as multiple threads may simultaneously use processor resources. Multiple threads are concurrently executed in an SMT processor so that multiple processor execution units, such as floating point units, fixed point instruction units, load/store units and others can be performing tasks for one (or more depending on the execution units' capabilities) of multiple threads simultaneously. SMT processors also may simultaneously use external resources, such as memory and peripheral devices. The simultaneous use raises the difficulty of determining how resources are used by an individual thread, as within a given execution slice, multiple threads may access an external device.
The above-incorporated patent applications disclose methods and systems for energy management that provide a fine level of control of power use by memory modules and other devices within a processing system by providing device controllers that measure the use of a resource and automatically take the resource off-line (i.e., place the device in a power saving state or cut power to the device), when the device is being infrequently accessed, or is likely to be infrequently accessed based on a next scheduled process. The power management schemes disclosed in the above-incorporated patent applications include per-process measurement of device usage in order to inform the energy management decision making process. However, in an SMT system, the scheduler will schedule execution of multiple threads at each execution slice, and so the assumption of per-process collection of information based on measuring device usage during is no longer accurate, as multiple threads can access the same device such as a memory module during a given execution slice and when another execution slice is scheduled, the same threads may not be executing.
It is therefore desirable to provide a method and system for providing energy management within an SMT processing system, that can reduce power consumption by placing resources that are used infrequently for a given “next” thread set in a power-saving state, while providing high processing throughput by maintaining low resource latency for resources that are likely to be used frequently for the next thread set.